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200 mhz dual integrated dcl with level setting dacs, per pin pmu, and per chip vhh ADATE304 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features driver 3-level driver with high-z mode and built-in clamps precision trimmed output resistance low leakage mode (typically <10 na) voltage range: up to ?2.0 v to +6.0 v 2.4 ns minimum pulse width, 2 v terminated comparator window and differential comparator 500 mhz input equivalent bandwidth load 12 ma maximum current capability per pin pmu force voltage range: up to ?2.0 v to +6.0 v 5 current ranges: 32 ma, 2 ma, 200 a, 20 a, 2 a levels 14-bit dac for dcl levels typically < 5 mv inl (calibrated) 16-bit dac for pmu levels typically < 1.5 mv inl (calibrated) linearity in fv mode hvout output buffer 0 v to 13.5 v output range 84-lead, 9 mm 9 mm, csp_bga package 900 mw per channel with no load applications automatic test equipment semiconductor test systems board test systems instrumentation and characterization equipment general description the ADATE304 is a complete, single-chip solution that performs the pin electronic functions of the driver, the comparator, and the active load (dcl), per pin pmu, and dc levels for ate appli- cations. the device also contains an hvout driver with a vhh buffer capable of generating up to 13.5 v. the driver features three active states: data high mode, data low mode, and term mode, as well as an inhibit state. the inhibit state, in conjunction with the integrated dynamic clamp, facili- tates the implementation of a high speed active termination. the ADATE304 supports two output voltage ranges: ?2.0 v to +6.0 v and ?1.25 v to +6.75 v by adjusting the positive and negative supply voltages. each channel of the ADATE304 features a high speed window comparator per pin for functional testing, as well as a per pin pmu with fv, or fi and mv, or mi functions. all necessary dc levels for dcl functions are generated by on-chip 14-bit dacs. the per pin pmu features an on-chip 16-bit dac for high accuracy and contains integrated range resistors to minimize external component counts. the ADATE304 uses a serial bus to program all functional blocks and has an on-board temperature sensor for monitoring the device temperature.
ADATE304 rev. 0 | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 total function ............................................................................... 4 driver ............................................................................................. 5 reflection clamp .......................................................................... 7 normal window comparator .................................................... 7 differential comparator .............................................................. 9 active load .................................................................................. 10 pmu ............................................................................................. 11 external sense (pmus_chx) ................................................... 16 dutgnd input ......................................................................... 16 serial peripheral interface ......................................................... 16 hvout driver ........................................................................... 17 overvoltage detector (ovd) ................................................... 18 16-bit dac monitor mux ....................................................... 18 absolute maximum ratings .......................................................... 19 thermal resistance .................................................................... 19 explanation of test levels ......................................................... 19 esd caution................................................................................ 19 pin configuration and function descriptions ........................... 20 typical performance characteristics ........................................... 23 spi details ....................................................................................... 33 definition of spi word .............................................................. 34 write operation.......................................................................... 35 read operation........................................................................... 36 reset operation .......................................................................... 37 register map ................................................................................... 38 details of registers ......................................................................... 39 user information ............................................................................ 41 power supply considerations ................................................... 41 truth tables................................................................................. 41 details of dacs vs. levels ......................................................... 43 recommended pmu mode switching sequences ................. 45 block diagrams ............................................................................... 47 outline dimensions ....................................................................... 51 ordering guide .......................................................................... 51 revision history 10/08revision 0: initial version
ADATE304 rev. 0 | page 3 of 52 functional block diagram 16-bit dac pmu pmu_flag mux * mux * window diff. c * vhh drv 14-bit dac ovd temperature sensor * vol voh c c other channel dut1 force sense r out (trimmed) vclamph vclampl vclamph vclampl iol ioh vcom spi * 50? 100 ? 100? vh vt vl ch1 ch1 dac16_mon measout01 pmus_ch0 data0p data0n rcv0p rcv0n comp_qh0p comp_vtt0 comp_qh0n comp_ql0p tempsense hvout dut0 ovd_ch0 comp_ql0n sdin rst sclk cs sdout ADATE304 g * mux * one per device. * 07279-001 figure 1. one of two channels
ADATE304 rev. 0 | page 4 of 52 specifications characterization and production tests performed using power supply range 1 (see table 37). v dd = +10.75 v, v cc = +3.3 v, v ss = ?5.00 v, v plus = +16.75 v, v comp_vtt = +3.3 v, v ref = +5.0 v, v ref_gnd = 0.0 v. all default test conditions are as defined in table 38. all specified values are at t j = 55c, where t j corresponds to the internal temperature sensor and the temperature coefficients are measured at t j = 55c 20c, unless otherwise noted. typical values are based on design, simulation analyses, and/or limited bench evaluations. typical values are not tested or guaranteed. test levels are specified in the explanation of test levels section. total function table 1. parameter symbol min typ max unit test level test conditions/comments total function output leakage current pe disable range e ?20.0 +5.3 +20.0 na p ?1.25 v < v dutx < +6.0 v; pmu and pe disabled via spi; pmu range e, vch = 7.0 v, vcl = ?2.5 v pe disable range a to range d 5.3 na c t ?1.25 v < v dutx < +6.0 v; pmu and pe disabled via spi; pmu range a, pmu range b, pmu range c, and pmu range d, vch = +7.0 v, vcl = ?2.5 v high-z mode ?400 +5.4 +400 na p ?1.25 v < v dutx < +6.0 v; pmu disabled and pe enabled via spi; rcv active, vch = +7.0 v, vcl = ?2.5 v output capacitance 4 pf s vterm mode operation dut pin range ?1.25 +6.0 v d power supplies total supply range, v plus to v ss 22.5 23.25 v d defines psrr conditions vplus supply v plus 16.25 16.75 17.25 v d defines psrr conditions positive supply v dd 10.25 10.75 11.25 v d defines psrr conditions negative supply v ss ?5.25 ?5.00 ?4.75 v d defines psrr conditions logic supply v cc 3.1 3.3 3.5 v d defines psrr conditions comparator termination v comp_vtt 3.3 5.0 v d v plus supply current i plus ?1.0 +1.3 +3.0 ma p hvout disabled 4.0 12.7 16.0 ma p hvout enabled, rcv active, no load, vhh = 12 v logic supply current i cc 1.0 2.7 4.0 ma p quiescent (spi is static) comparator termination current i comp_vtt 10.0 17 26.0 ma p positive supply current i dd 72 90.5 97 ma p load power down (ioh = iol = 0 ma) negative supply current i ss 100 116 126 ma p load power down (ioh = iol = 0 ma) total power dissipation 1. 0 1.6 1.82 w p load power down (ioh = iol = 0 ma) positive supply current i dd 102 120 152 ma p load active off (ioh = iol = 12 ma) negative supply current i ss 130 146 181 ma p load active off (ioh = iol = 12 ma) total power dissipation 1. 8 2.2 2.5 w p load active off (ioh = iol = 12 ma) temperature monitors temperature sensor gain 10 mv/k c t temperature sensor accuracy without calibration over 25c to 100c 6 c c t temperature voltage available on pin a1 at all times and on pin k1 (measout01/tempsense) when selected (see table 24 and table 36 ) vref input reference input voltage range for dacs (vref pin) 4.95 5 5.05 v d referenced to v ref_gnd ; not referenced to v dutgnd input bias current 0.1 100 a p tested with 5 v applied
ADATE304 rev. 0 | page 5 of 52 driver vh ? vl 200 mv (to meet dc and ac specifications). table 2. parameter min typ max unit test level test conditions/comments dc specifications high speed differential logic input characteristics (dataxx, rcvxx) input termination resistance 92 100 108 p push 6 ma into xp pins 1 , force 1.3 v on xn pins 1 ; measure voltage from xp to xn 1 , calculate resistance (v/i) input voltage differential 0.2 1.0 v p f common-mode voltage 0.85 2.35 v p f 0.85 3.5 v d input bias current ?20.0 +2.2 +20.0 a p each pin te sted at 2.85 v and 0.35 v while the other high speed pin remains open pin output characteristics output high range, vh ?1.15 +6.75 v d output low range, vl ?1.25 +6.65 v d output term range, vt ?1.25 +6.75 v d functional amplitude (vh ? vl) 0.0 8.0 v d amplit ude can be programmed to vh = vl, accuracy specifica- tions apply when vh ? vl 200 mv dc output current limit source 75 100 120 ma p driver high, vh = 6.75 v, short dutx pin to ?1.25 v, measure current dc output current limit sink ?120 ?100 ?75 ma p driver low, vl = ?1.25 v, short dutx pin to +6.75 v, measure current output resistance, 50 ma 45.0 47.0 49.0 p source: driver high, vh = +3.0 v, i dutx = +1 ma and +50 ma; sink: driver low, vl = 0.0 v, i dutx = ?1 ma and ?50 ma; v dut /i dut absolute accuracy vh tests done with vl = ?2.5 v and vt= ?2.5 v; vl tests done with vh = +7.5 v and vt = +7.5 v; vt tests done with vl = ?2.5 v and vh = +7.5 v; unless otherwise specified vh, vl, vt uncalibrated accuracy ?250 75 +250 mv p e rror measured at calibration points of 0 v and 5 v vh, vl, vt offset tempco 450 v/c c t measured at calibration points vh, vl, vt dnl 1 mv c t after two-point gain/offset calibration vh, vl, vt inl ?10 2.5 +10 mv p after two-point gain/offset cali bration; measured over driver output ranges vh, vl, vt resolution 0.6 +1 mv p f after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 0 v and 5 v dutgnd voltage accuracy ?7 1.3 +7 mv p over 0.1 v range; measured at endp oints of vh, vl, and vt functional range vh, vl, vt crosstalk 2 mv c t vl = ?1.25 v: vh = ?1.15 v +6.75 v, vt = ?1.25 v +6.75 v; vh = +6.75 v: vl = ?1.25 v +6.65 v, vt = ?1.25 v +6.75 v; vt = +1.25 v: vl = ?1.25 v +6.65 v, vh = ?1.15 v +6.75 v; dc crosstalk on vl, vh, vt output level when other driver dacs are varied overall voltage accuracy 10 mv c t sum of inl, crosstalk, dutgnd, and tempco over 5c, after gain/offset calibration vh, vl, vt dc psrr 15 mv/v c t measured at calibration points ac specifications rise/fall times toggle dataxx 0.2 v programmed swing 950 ps c b vh = 0.2 v, vl = 0.0 v, terminated; 20% to 80% 1.0 v programmed swing 850 ps c b vh = 1.0 v, vl = 0.0 v, terminated; 20% to 80% 2.0 v programmed swing 850 1150 1350 ps c b vh = 3.0 v, vl = 0.0 v, terminated; 20% to 80% 3.0 v programmed swing 1500 ps p/c b vh = 3.0 v, vl = 0.0 v, terminated; 20% to 80% 3.0 v programmed swing 2000 ps c b vh = 3.0 v, vl = 0.0 v, unterminated; 10% to 90% 5.0 v programmed swing 3100 ps c b vh = 5.0v, vl = 0.0 v, unterminated; 10% to 90% rise-to-fall matching 40 ps c b vh = 3.0 v, vl = 0.0 v, terminated; rise-to-fall within one channel
ADATE304 rev. 0 | page 6 of 52 parameter min typ max unit test level test conditions/comments minimum pulse width toggle dataxx 1.0 v programmed swing 1.7 ns c b vh = 1.0 v, vl = 0.0 v, terminated; timing error 75 ps 1.7 ns c b vh = 1.0 v, vl = 0.0 v, terminated; less than 10% amplitude degradation 2.0 v programmed swing 2.0 ns c b vh = 2.0 v, vl = 0.0 v, terminated; timing error 75 ps 2.2 ns c b vh = 2.0 v, vl = 0.0 v, terminated; less than 10% amplitude degradation 3.0 v programmed swing 2.7 ns c b vh = 3.0 v, vl = 0.0 v, terminated; timing error 75 ps 2.7 ns c b vh = 3.0 v, vl = 0.0 v, terminated; less than 10% amplitude degradation maximum toggle rate 2.0 v programmed swing 200 mhz c b vh = 2.0 v, vh = 0.0 v, terminated, 10% amplitude degradation dynamic performance, drive (vh to vl and vl to vh) toggle dataxx propagation delay time 3.0 ns c b vh = 2.0 v, vl = 0.0 v, terminated propagation delay tempco 3.0 ps/c c t vh = 2.0 v, vl = 0.0 v, terminated delay matching vh = 2.0 v, vl = 0.0 v, terminated edge to edge 80 ps c b rising vs. falling channel to channel 30 ps c b rising vs. rising, falling vs. falling delay change vs. duty cycle 30 ps c b vh = 3.0 v, vl = 0.0 v, terminated; 5% to 95% duty cycle; 1 mhz overshoot and undershoot 30 mv c b vh = 3.0 v, vl = 0.0 v, terminated settling time (vh to vl) toggle dataxx to within 3% of final value 4 ns c b vh = 3.0 v, vl = 0.0 v, terminated to within 1% of final value 25 ns c b vh = 3.0 v, vl = 0.0 v, terminated dynamic performance, vt (vh or vl to vt and vt to vh or vl) toggle rcvxx propagation delay time 3.7 ns c b vh = 3.0 v, vt = 1.5 v, vl = 0.0 v, terminated delay matching, edge to edge 150 ps c b vh = 3.0 v, vt = 1.5 v, vl = 0. 0 v, terminated; rising vs. falling propagation delay tempco 4.0 ps/c c t vh = 3.0 v, vt = 1.5 v, vl = 0.0 v, terminated transition time, active to vt and vt to active 1.0 ns c b vh = 3.0 v, vt = 1.5 v, vl = 0.0 v, terminated; 20% to 80% dynamic performance, inhibit (vh or vl to/from inhibit) toggle rcvxx propagation delay time vh = +1.0 v, vl = ?1.0 v, terminated active to inhibit 4.5 ns c b inhibit to active 7.9 ns c b transition time vh =+1.0 v, vl = ?1.0 v, terminated; 20% to 80% active to inhibit 2.9 ns c b inhibit to active 0.65 ns c b i/o spike 190 mv c b vh = 0.0 v, vl = 0.0 v, terminated 1 the xp pins include data0p, data1p, rcv0p, and rcv1p; the xn pins include data0n, data1n, rcv0n, and rcv1n. for example, push 6 ma into the data0p pin, force 1.3 v into data0n, and measure the voltage from data0p to data0n.
ADATE304 rev. 0 | page 7 of 52 reflection clamp clamp accuracy specifications apply when vch > vcl. table 3. parameter min typ max unit test level test conditions/comments vch range ?1.0 +6.75 v d uncalibrated accuracy ?200 50 +200 mv p driver hi gh-z, sinking 1 ma; vch error measured at the calibration points of 0.0 v and 5.0 v resolution 0.6 0.75 mv p f driver high-z, sinking 1 ma ; after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points of 0.0 v and 5.0 v dnl 1 mv c t driver high-z, sinking 1 ma ; after two-point gain/offset calibration inl ?40 2 +40 mv p driver high-z, sin king 1 ma; after two-point gain/offset calibration; measured over vch range of ?1.0 v to +6.75 v tempco ?0.3 mv/c c t measured at calibration points vcl range ?1.25 +5.75 v d uncalibrated accuracy ?200 50 +200 mv p driver hi gh-z, sourcing 1 ma; vcl error measured at the calibration points of 0.0 v and 5.0 v resolution 0.6 0.75 mv p f driver high-z, sourcing 1 ma ; after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points of 0.0 v and 5.0 v dnl 1 mv c t driver high-z, sourcing 1 ma ; after two-point gain/offset calibration inl ?40 2 +40 mv p driver high-z, sour cing 1 ma; after two-point gain/offset calibration; measured over vcl range of ?1.0 v to +5.75 v tempco 0.5 mv/c c t measured at calibration points dc clamp current limit vch ?120 ?85 ?60 ma p driver high-z, vch = 0 v, vcl = ?1.0 v, v dutx = +5 v vcl 60 85 120 ma p driver high-z, vch = 6.75 v, vcl = 5.0 v, v dutx = 0.0 v dutgnd voltage accuracy ?7 1 +7 mv p over 0.1 v range; measured at the endpoints of vch and vcl functional range normal window comparator voh tests done with vol = ?1.25 v; vol tests done with voh = 6.0 v, unless otherwise specified. table 4. parameter min typ max unit test level test conditions/comments dc specifications input voltage range ?1.25 +6.75 v d differential voltage range 0.1 8.0 v d comparator input offset voltage accuracy, uncalibrated ?150 30 +150 mv p offset measured at the calibration points of 0.0 v and 5.0 v comparator threshold resolution 0.6 1 mv p f after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points of 0 v and 5 v comparator threshold dnl 1 mv c t after two-point gain/offset calibration comparator threshold inl ?7 1.3 +7 mv p after two-point gain/offset calibration; measured over voh, vol range of ?1.25 v to +6.75 v comparator input offset voltage tempco 100 v/c c t measured at calibration points dutgnd voltage accuracy ?7 0.5 +7 mv p over 0.1 v range; measured at endpoints of voh and vol functional range
ADATE304 rev. 0 | page 8 of 52 parameter min typ max unit test level test conditions/comments comparator uncertainty range 6.0 mv c b v dutx = 0 v, sweep comparator threshold to determine uncertainty region dc hysteresis 0.5 mv c b v dutx = 0 v dc psrr 5 mv/v c t measured at calibration points digital output characteristics internal pull-up resistance to comparator, comp_vtt pin 40 50 60 p pull 1 ma and 10 ma from logic 1 leg and measure v to calculate resistance; measured v/9 ma; done for both comparator logic states v comp_vtt range 3.3 5.0 v d common-mode voltage v comp_vtt ? 1.88 v c t measured with 100 differential termination v comp_vtt ? 2.075 v comp_vtt ? 1.675 v p measured with no external termination differential voltage 250 mv c t measured with 100 differential termination 400 500 600 mv p measured with no external termination rise/fall time, 20% to 80% 450 ps c b measured with each comparator leg terminated 50 to gnd ac specifications input tran sition time = 800 ps, 10% to 90%; measured with each comparator leg terminated 50 to gnd, unless otherwise specified propagation delay, input to output 1.75 ns c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = +0.50 v, vol = ?1.25 v; low-side measurement: voh = +6.75 v, vol = +0.50 v propagation delay tempco 5 ps/c c t v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = +0.50 v, vol = ?1.25 v; low-side measurement: voh = +6.75 v, vol = +0.50 v propagation delay matching v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = +0.50 v, vol = ?1.25 v; low-side measurement: voh = +6.75 v, vol = +0.50 v high transition to low transition 200 ps c b high to low comparator 50 ps c b propagation delay change (with respect to) slew rate, 800 ps, 1 ns, 1.2 ns, and 2.2 ns (10% to 90%) 50 ps c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = +0.50 v, vol = ?1.25 v; low-side measurement: voh = +6.75v, vol = +0.50 v overdrive, 250 mv and 1.0 v 75 ps c b for 250 mv: v dutx = 0 v to 0.5 v swing; for 1.0 v: v dutx = 0 v to 1.25 v swing; driver vterm mode, vt = 0.0 v; high-side measurement: voh = +0.25 v, vol = ?1.25 v; low-side measurement: voh = +6.75 v, vol = +0.25 v pulse width, sweep 1.6 ns to 10 ns 75 ps c b v dutx = 0 v to 1.0 v swing @ 32.0 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = +0.5 v, vol = ?1.25 v; low-side measurement: voh = +6.75 v, vol = +0.5 v duty cycle, 5% to 95% 50 ps c b v dutx = 0 v to 1.0 v swing @ 1.0 mhz, driver vterm mode, vt =0.0 v; high-side measurement: voh = +0.50 v, vol = ?1.25 v; low-side measurement: voh = +6.75 v, vol = +0.50 v minimum pulse width 2.0 ns c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; less than 12% amplitude degradation measured by shmoo input equivalent bandwidth, terminated 500 mhz c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; as measured by shmoo ert high-z mode, 3 v, 20% to 80% 2.5 ns c b v dutx = 0 v to 3.0 v swing, driver high-z; as measured by shmoo; input transition time of ~2000 ps, 10% to 90%
ADATE304 rev. 0 | page 9 of 52 differential comparator voh tests done with vol = ?1.1 v, vol tests done with voh = +1.1 v, unless otherwise specified. table 5. parameter min typ max unit test level test conditions/comments dc specifications input voltage range ?1.25 +4.5 v d operational differential voltage range 0.05 1.1 v d maximum differential voltage range 8 v d comparator input offset voltage accuracy, uncalibrated ?150 35 +150 mv p/c t offset measured at different ial calibration points +1.0 v and ?1.0 v, with common mode = 0.0 v voh, vol resolution 0.6 1 mv p f after two-point gain/offset calibration; range/number of dac bits as measured at differential calibration points +1.0 v and ?1.0 v, with common mode = 0.0 v voh, vol dnl 1 mv c t after two-point gain/offset calibration; common mode = 0.0 v voh, vol inl ?15 2.0 +15 mv p after two-point gain/offset calibration; measured over voh, vol range of ?1.1 v to +1.1 v, common mode = 0.0 v voh, vol offset voltage tempco 200 v/c c t measured at calibration points comparator uncertainty range 18 mv c b v dutx = 0 v, sweep comparator threshold to determine uncertainty region dc hysteresis 0.5 mv c b v dutx = 0 v cmrr 0.15 1 mv/v p offset measured at common-mode voltage points of ?1.5 v and +4.5 v, with differential voltage = 0.0 v dc psrr 1.5 mv/v c t measured at calibration points ac specifications input transition time = 800 ps, 10% to 90%, measured with each comparator leg terminated 50 to gnd propagation delay, input to output 1.7 ns c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel propagation delay tempco 5 ps/c c t v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel propagation delay matching v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel high transition to low transition 100 ps c b high-to-low comparator 50 ps c b propagation delay change (with respect to) v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel slew rate, 800 ps, 1 ns, 1.2 ns, and 2.2 ns (10% to 90%) 60 ps c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel overdrive, 250 mv and 750 mv 100 ps c b v dut0 = 0 v, for 250 mv: v dut1 = 0 v to 0.5 v swing; for 750 mv: v dut1 = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; voh = ?0.25 v; repeat for other dut channel with comparator threshold = +0.25 v pulse width, sweep from 1.6 ns to 10 ns 75 ps c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing @ 32 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel duty cycle, 5% to 95% 60 ps c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing @ 1 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; repeat for other dut channel
ADATE304 rev. 0 | page 10 of 52 parameter min typ max unit test level test conditions/comments minimum pulse width 2.5 ns c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; less than 10% amplitude degradation measured by shmoo; repeat for other dut channel input equivalent bandwidth, terminated 400 mhz c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = +1.1 v, vol = 0.0 v; less than 22% amplitude degradation measured by shmoo; repeat for other dut channel active load see the tr uth tables section and table 29 for load control information. table 6. parameter min typ max unit test level test conditions/comments dc specifications load active on, rcv active, unless otherwise noted input characteristics vcom voltage range ?1.00 +6.50 v d v dut range ?1.25 +6.75 v d vcom accuracy, uncalibrated ?200 30 +200 mv p ioh = iol = 6 ma, vcom error measured at the calibration points of 0.0 v and 5.0 v vcom resolution 0.6 1 mv p f ioh = iol = 6 ma, after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points of 0.0 v and 5.0 v vcom dnl 1 mv c t ioh = iol = 6 ma, after two-point gain/offset calibration vcom inl ?7 2 +7 mv p ioh = iol = 6 ma, after two-point gain/offset calibration; measured over vcom range of ?1.00 v to +6.50 v dutgnd voltage accuracy ?7 1 +7 mv p over 0.1 v range; measured at end points of vcom functional range output characteristics iol maximum source current 12 ma d uncalibrated offset ?600 100 +600 a p ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, iol offset calculated from the calibration points of 1 ma and 11 ma uncalibrated gain ?12 4 +12 % p ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, iol gain calculated from the calibration points of 1 ma and 11 ma resolution 1.5 2 a p f ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, after two-point gain/ offset calibration; range/number of dac bits as measured at the calibration points of 1 ma and 11 ma dnl 3.0 a c t ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, after two-point gain/offset calibration inl ?80 20 +80 a p ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, after two-point gain/ offset calibration; measured over iol range of 0 ma to 12 ma 90% commutation voltage 0.25 v p ioh = iol = 12 ma, vcom = 2.0 v, measure iol reference at v dutx = ?1.0 v, measure iol current at v dutx = +1.75 v, ensure > 90% of reference current ioh maximum sink current 12 ma d uncalibrated offset ?600 100 +600 a p iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, ioh offset calculated from the calibration points of 1 ma and 11 ma uncalibrated gain ?12 4 +12 % p iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, ioh gain calculated from the calibration points of 1 ma and 11 ma resolution 1.5 2 a p f iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points of 1 ma and 11 ma dnl 3.0 a c t iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, after two-point gain/offset calibration
ADATE304 rev. 0 | page 11 of 52 parameter min typ max unit test level test conditions/comments inl ?80 20 +80 a p iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, after two-point gain/ offset calibration; measured over ioh range of 0 ma to 12 ma 90% commutation voltage 0.25 v p ioh = iol =1 2 ma, vcom = 2.0 v, measure ioh reference at v dutx = 5.0 v, measure ioh current at v dutx = 2.25 v, ensure > 90% of reference current output current tempco 1.5 a/c c t measured at calibration points ac specifications load active on, unless otherwise noted dynamic performance propagation delay, load active on to load active off; 50%,90% 7.3 ns c b toggle rcv, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; measured from 50% point of rcvxp ? rcvxn to 90% point of final output, repeat for drive low and high propagation delay, load active off to load active on; 50%, 90% 10.3 ns c b toggle rcv, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; measured from 50% point of rcvxp ? rcvxn to 90% point of final output, repeat for drive low and high propagation delay matching 3.0 ns c b toggle rcv, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; active on vs. active off, repeat for drive low and high load spike 190 mv c b toggle rcv, dutx terminated 50 to gnd, ioh = iol = 0 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; repeat for drive low and high settling time to 90% 1.9 ns c b toggle rcv, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; measured at 90% of final value pmu fv is the force voltage, mv is the measure voltage, fi is the force current, mi is the measure current, fn is force nothing. table 7. parameter min typ max unit test level test conditions/comments force voltage (fv) current range a 32 ma d current range b 2 ma d current range c 200 a d current range d 20 a d current range e 2 a d force input voltage range at output for all ranges ?1.25 +6.75 v d force voltage uncalibrated accuracy for range c ?100 25 +100 mv p pmu enabled, fv, rang e c, pe disabled, error measured at calibration points of 0.0 v and 5.0 v force voltage uncalibrated accuracy for all ranges 25 mv c t pmu enabled, fv, pe disabled, error measured at calibration points of 0.0 v and 5.0 v; repeat for each pmu current range force voltage offset tempco for all ranges 25 v/c c t measured at calibration points for each pmu current range force voltage gain tempco for all ranges 10 ppm/c c t measured at calibration points for each pmu current range forced voltage inl ?7 2 +7 mv p pmu enabled, fv, range c, pe disabled, after two-point gain/offset calibration; measured over output range of ?1.25 v to +6.75 v force voltage compliance vs. current load pmu enabled, fv, pe disabled, force ?1.25 v, measure voltage while pmu sinking zero and full-scale current; measure ?v; force 6.75 v, measure voltage while pmu sourcing zero and full-scale current; measure ?v; repeat for each pmu current range range a 4 mv c t range b to range e 1 mv c t
ADATE304 rev. 0 | page 12 of 52 parameter min typ max unit test level test conditions/comments current limit, source, and sink range a 108 140 180 %fs p pmu enabled, fv, pe disabled; sink: force 2.5 v, short dutx to 6.0 v; source: force 2.5 v, shor t dutx to ?1.0 v; range a fs = 32 ma, 108% fs = 35 ma, 180% fs = 58 ma range b to range e 120 145 180 %fs p pmu enabled, fv , pe disabled; sink: force 2.5 v, short dutx to 6.0 v; source: force 2.5 v, short dutx to ?1.0 v; repeat for each pmu current range; example: range b fs = 2 ma, 120 % fs = 2.4 ma, 180% fs = 3.6 ma dutgnd voltage accuracy ?7 1 +7 mv p over 0.1 v range; measured at endpoints of fv functional range measure current (mi) v dutx externally forced to 0.0v, un less otherwise specified; ideal measout transfer functions: v measout01 [v] = (i measout01 5/fsr) + 2.5 + v dutgnd i(v measout01 ) [a] = (v measout01 ? v dutgnd ? 2.5) fsr/5 measure current, pin dutx voltage range for all ranges ?1.5 +6.0 v d measure current uncalibrated accuracy range a 500 a c t pmu enabled, fimi, range a, pe disabled, error at calibration points ?25 ma and +25 ma, error = (i(v measout01 ) ? i dutx ) range b ?400 3.0 +400 a p pmu enabled, fimi, range b, pe disabled, error at calibration points ?1.6 ma and +1.6 ma, error = (i(v measout01 ) ? i dutx ) range c 2.00 a c t pmu enabled, fimi, pe disabled, error at calibration points of 80% fs, error = (i(v measout01 ) 1 ? i dutx ) range d 0.30 a c t pmu enabled, fimi, pe disabled, error at calibration points of 80% fs, error = (i(v measout01 ) ? i dutx ) range e 0.08 a c t pmu enabled, fimi, pe disabled, error at calibration points of 80% fs, error = (i(v measout01 ) ? i dutx ) measure current offset tempco range a 2 a/c c t measured at calibration points range b 25 na/c c t measured at calibration points range c 5 na/c c t measured at calibration points range d and range e 1 na/c c t measured at calibration points measure current gain error, nominal gain = 1 range a 2.5 % c t pmu enabled, fimi, pe disabled, gain error from calibration points 80% fs range b ?20 2 +20 % p pmu enabled, fimi, range b, pe disabled, gain error from calibration points 1.6 ma range c to range e 4 % c t pmu enabled, fimi, pe disabled, gain error from calibration points 80% fs measure current gain tempco measured at calibration points range a 300 ppm/c c t range b to range e 50 ppm/c c t measure current inl range a 0.05 %fsr c t pmu enabled, fimi, range a, pe disabled, after two-point gain/offset calibration, measured over fsr output of ?32 ma to +32 ma range b ?0.02 +0.02 %fsr p pmu enabled, fim, i range b, pe disabled, after two-point gain/ offset calibration measured over fsr output of ?2 ma to +2 ma range b to range e 0.01 %fsr c t pmu enabled, fimi, pe disabl ed, after two-point gain/offset calibration; measured over fsr output fvmi dut pin voltage rejection ?0.01 +0.01 %fsr/v p pmu en abled, fvmi, range b, pe disabled, force ?1 v and +5 v into load of 1 ma; measure ?i reported at measout01 dutgnd voltage accuracy 2.5 mv c t over 0.1 v range; measured at endpoints of mi functional range
ADATE304 rev. 0 | page 13 of 52 parameter min typ max unit test level test conditions/comments force current (fi) v dutx externally forced to 0.0v, un less otherwise specified, ideal force current transfer function: i force = (pmudac ? 2.5) (fsr/5) force current, dutx pin voltage range for all ranges ?1.25 +6.75 v d force current uncalibrated accuracy range a ?5.0 0.5 +5.0 ma p pmu enabled, fimi , range a, pe disabled, error at calibration points of ?25 ma and +25 ma range b ?400 40 +400 a p pmu enabled, fimi, range b, pe disabled, error at calibration points of ?1.6 ma and 1.6 ma range c ?40 4 +40 a p pmu enabled, fimi, range c, pe disabled, error at calibration points of 80% fs range d ?4 0.4 +4 a p pmu enabled, fimi, range d, pe disabled, error at calibration points of 80% fs range e ?400 75 +400 na p pmu enabled, fimi, range e, pe disabled, error at calibration points of 80% fs force current offset tempco range a 1 a/c c t measured at calibration points range b 80 na/c c t measured at calibration points range c to range e 4 na/c c t measured at calibration points forced current gain error, nominal gain = 1 ?20 4 +20 % p pmu enabled, fimi, pe disabled, gain error from calibration points of 80% fs forced current gain tempco measured at calibration points range a ?500 ppm/c c t range b to range e 75 ppm/c c t force current inl range a ?0.3 0.05 +0.3 %fsr p pmu enabled, fimi, range a, pe disabled, after two-point gain/offset calibration; measured over fsr output of ?32 ma to +32 ma range b to range e ?0.2 0.015 +0.2 %fsr p pmu enab led, fimi, pe disabled, af ter two-point gain/offset calibration; measured over fsr output force current compliance vs. voltage load pmu enabled, fimv, pe d isabled; force positive full-scale current driving ?1.5 v and +6.0 v, measure ?i @ dutx pin; force negative full-scale current driving ?1.25 v and +6.75 v, measure ?i @ dutx pin range a to range d ?0.6 0.06 +0.6 %fsr p range e ?1.0 0.1 +1.0 %fsr p measure voltage measure voltage range ?1.5 +6.0 v d measure voltage uncalibrated accuracy ?25 2.0 +25 mv p pmu enabled, fvmv, range b, pe disabled, error at calibration points of 0 v and 5 v, error = (v measout01 ? v dutx ) measure voltage offset tempco 10 v/c c t measured at calibration points measure voltage gain error ?0.2 0.01 +0.2 % p pmu en abled, fvmv, range b, pe disabled, gain error from calibration points of 0 v and 5 v measure voltage gain te mpco 25 ppm/c c t measured at calibration points measure voltage inl ?7 1 +7 mv p pmu enabled, fvmv, range b, pe disabled, after two-point gain/offset calibration; measured over output range of ?1.25 v to +6.75 v rejection of measure v vs. i dutx ?1.5 0.1 +1.5 mv p pmu enabled, fvmv, range d, pe disabled, force 0 v into load of ?10 a and +10 a; measure ?v reported at measout01
ADATE304 rev. 0 | page 14 of 52 parameter min typ max unit test level test conditions/comments measout01 dc characteristics measout01 voltage range ?1.5 +6.0 v d d c output current 4 ma d measout01 pin output impedance 25 200 p pmu enabled, fvmv, pe disabled; source resistance: pmu force +6.75 v and load with 0 ma and +4 ma; sink resistance: pmu force ?1.25 v and load with 0 ma and ?4 ma; resistance = ?v/?i at measout01 pin output leakage current when tristated ?1 +1 a p tested at ?1.25 v and +6.75 v output short-circuit current ?25 +25 ma p pmu enab led, fvmv, pe disabled; source: pmu force +6.75 v, short measout01 to ?1.25 v; sink: pmu force ?1.25 v, short measout01 to +6.75 v voltage clamps low clamp range (vcl) ?1.25 +4.75 v d high clamp range (vch) 0.75 6.75 v d positive clamp voltage droop ?300 +10 +300 mv p pmu enabled, fimi, range a, pe disabled, pmu clamps enabled, vch = +5.0 v, vcl = ?1.0 v, pmu force 2.0 ma and 32 ma into open; ?v seen at dutx pin negative clamp voltage droop ?300 ?10 +300 mv p pmu enabled, fimi, range a, pe disabled, pmu clamps enabled, vch = +5.0 v, vcl = ?1.0 v, pmu force ?2.0 ma and ?32 ma into open; ?v seen at dutx pin uncalibrated accuracy ?250 100 +250 mv p pmu enabled, fimi, range b, pe disabled, pmu clamps enabled, pmu force 1 ma into open; vch errors at calibration points 1.0 v and 5.0 v; vcl errors at the calibration points 0.0 v and 4.0 v inl ?70 5 +70 mv p pmu enabled, fimi, range b, pe disabled, pmu clamps enabled, pmu force 1 ma into open; after two-point gain/offset calibration; measured over pmu clamp range dutgnd voltage accuracy 1 mv c t over 0.1 v range; measured at endpoints of pmu clamp functional range settling/switching times scap = 330 pf, ffcap = 220 pf voltage force settling time to 0.1% of final value pmu enabled, fv, pe disabled, program pmudac steps of 500 mv and 5.0 v; simulation of worst case, 2000 pf load, pmudac step of 5.0 v range a, 200 pf and 2000 pf load 15 s s range b, 200 pf and 2000 pf load 20 s s range c, 200 pf and 2000 pf load 124 s s range d, 200 pf and 2000 pf load 1015 s s range e, 200 pf and 2000 pf load 3455 s s voltage force settling time to 1.0% of final value pmu enabled, fv, pe disabled, start with pmudac programmed to 0.0 v, prog ram pmudac to 500 mv range a, 200 pf and 2000 pf load 14 s c b range b, 200 pf and 2000 pf load 14 s c b range c, 200 pf and 2000 pf load 14 s c b range d, 200 pf load 45 s c b range d, 2000 pf load 45 s c b range e, 200 pf load 45 s c b range e, 2000 pf load 225 s c b
ADATE304 rev. 0 | page 15 of 52 parameter min typ max unit test level test conditions/comments voltage force settling time to 1.0% of final value pmu enabled, fv, pe disabled, start with pmudac programmed to 0.0 v, pr ogram pmudac to 5.0 v range a, 200 pf and 2000 pf load 4.0 s c b range b, 200 pf load 4.2 s c b range b, 2000 pf load 4.2 s c b range c, 200 pf load 5.8 s c b range c, 2000 pf load 19 s c b range d, 200 pf load 50 s c b range d, 2000 pf load 210 s c b range e, 200 pf load 360 s c b range e, 2000 pf load 610 s c b current force settling time to 0.1% of final value pmu enabled, fi, pe disabled, start with pmudac programmed to 0 current, program pmudac to fs current range a, 200 pf in parallel with 120 8.2 s s range b, 200 pf in parallel with 1.5 k 9.4 s s range c, 200 pf in parallel with 15.0 k 30 s s range d, 200 pf in parallel with 150 k 281 s s range e, 200 pf in parallel with 1.5 m 2668 s s current force settling time to 1.0% of final value pmu enabled, fi, pe disabled, start with pmudac programmed to 0 current, program pmudac to fs current range a, 200 pf in parallel with 120 4.2 s c b range b, 200 pf in parallel with 1.5 k 4.3 s c b range c, 200 pf in parallel with 15.0 k 8.1 s c b range d, 200 pf in parallel with 150 k 205 s c b range e, 200 pf in parallel with 1.5 m 505 s c b interaction and crosstalk measure voltage channel-to- channel crosstalk 0.125 %fsr c t pmu enabled, fimv, pe disabled, range b, forcing 0 ma into 0 v load; other channel: range a, forcing a step of 0 ma to 25 ma into 0 v load; report ?v of measout01 pin under test; 0.125% 8.0 v = 10 mv measure current channel-to- channel crosstalk 0.01 %fsr c t pmu enabled, fvmi, pe disabled, range e, forcing 0 v into 0 ma current load; other channel: range e, forcing a step of 0 v to 5 v into 0 ma current load; report ?v of measout01 pin under test; 0.01% 5.0 v = 0.5 mv
ADATE304 rev. 0 | page 16 of 52 external sense (pmus_chx) table 8. parameter min typ max unit test level test conditions/comments external sense (pmus_chx) voltage range ?1.25 +6.75 v d input leakage current ?20 +20 na p tested at ?1.25 v and +6.75 v dutgnd input table 9. parameter min typ max unit test level test conditions/comments dutgnd input input voltage range, referenced to gnd ?0.1 +0.1 v d input bias current 1 100 a p tested at ?100 mv and +100 mv serial peripheral interface table 10. parameter min typ max unit test level test conditions/comments serial peripheral interface serial input logic high 1.8 v cc v p f serial input logic low 0 0.7 v p f input bias current ?10 1 +10 a p tested at 0.0 v and 3.3 v sclk clock rate 50 mhz p f sclk pulse width 9 ns c t sclk crosstalk on dutx pin 8 mv c b pe disabled, pmu fv enabled and forcing 0 v serial output logic high v cc ? 0.4 v cc v p f sourcing 2 ma serial output logic low 0 0.8 v p f sinking 2 ma update time 10 s d maximum delay time required for the part to enter a stable state after a serial bus
ADATE304 rev. 0 | page 17 of 52 hvout driver table 11. parameter min typ max unit test level test conditions/comments vhh buffer vhh = (vt + 1 v) 2 + dutgnd voltage range 5.9 v plus ? 3.25 v d v plus = 16.75 v nominal; in this condition, v hvout max = 13.5 v output high 13.5 v p vhh mode enabled, rcv active, vhh level = full scale, sourcing 15 ma output low 5.9 v p vhh mode enabled, rcv active, vhh level = zero scale, sinking 15 ma accuracy uncalibrated ?500 100 +500 mv p vhh mode enabled, rcv active, v hvout error measured at the calibration points of 7 v and 12 v offset tempco 1 mv/c c t measured at calibration points resolution 1.21 1.5 mv p f vhh mode enabled, rcv active, after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points of 7 v and 12 v inl ?30 15 +30 mv p vhh mode enabled, rcv active, after two-point gain/offset calibration; measured over vhh range of 5.9 v to 13.5 v dutgnd voltage accuracy 1 mv c t over 0.1 v range; measured at endpoints of vhh functional range output resistance 1 10 p vhh mode enabled, rcv active, source: vhh = 10.0 v, i hvout = 0 ma and 15 ma; sink: vhh = 6.5 v, i hvout = 0 ma and ?15 ma; ?v/?i dc output current limit source 60 100 ma p vhh mode enabled, rcv active, vhh = 10.0 v, short hvout pin to 5.9 v, measure current dc output current limit sink ?100 ?60 ma p vhh mo de enabled, rcv active, vhh = 6.5 v, short hvout pin to 14.1 v, measure current rise time (from vl or vh to vhh) 200 ns c b vhh mode enabled, toggle rcv, vhh = 13.5 v, vl = vh = 3.0 v; 20% to 80%, for data = high and data = low fall time (from vhh to vl or vh) 26 ns c b vhh mode enabled, toggle rcv, vhh = 13.5 v, vl = vh = 3.0 v; 20% to 80%, for data = high and data = low preshoot, overshoot, and undershoot 125 mv c b vhh mode enabled, toggle rcv, vhh = 13.5 v, vl = vh = 3.0 v; for data = high and data = low vl/vh buffer voltage range ?0.1 +6.0 v d accuracy uncalibrated ?500 100 +500 mv p vhh mode enabled, rcv inactive, error measured at the calibration points 0 v and 5 v offset tempco 1 mv/c c t measured at calibration points resolution 0.61 0.75 mv p f vhh mode enabled, rcv inactive, after two-point gain/offset calibration; range/number of dac bits as measured at the calibration points 0 v and 5 v inl ?20 4 +20 mv p vhh mode enabled, rcv inactive, after two-point gain/offset calibration; measured over range of ?0.1 v to +6.0 v dutgnd voltage accuracy 2 mv c t over 0.1 v range; measured at endpoints of vh and vl, functional range output resistance 45 48 50 p vhh mode enabled, rcv inactive, source: vh = 3.0 v, i hvout = +1 ma and +50 ma; sink: vl = 2.0 v, i hvout = ?1 ma and ?50 ma; ?v/?i dc output current limit source 60 100 ma p vhh mode enabled, rcv inactive, vh = +6.0 v, short hvout pin to ?0.1 v, data high, measure current dc output current limit sink ?100 ?60 ma p vhh mode enabled, rcv inactive, vl = ?0.1 v, short hvout pin to +6.0 v, data low, measure current rise time (vl to vh) 11 ns c b vhh mode enabled, rcv inactive, vl = 0.0 v, vh = 3.0 v, toggle data; 20% to 80% fall time (vh to vl) 11.3 ns c b vhh mode enabled, rcv inactive, vl = 0.0 v, vh = 3.0 v, toggle data; 20% to 80% preshoot, overshoot, and undershoot 54 mv c b vhh mode enabled, rcv inactive, vl = 0.0 v, vh = 3.0 v, toggle data
ADATE304 rev. 0 | page 18 of 52 overvoltage detector (ovd) table 12. parameter min typ max unit test level test conditions/comments dc characteristics programmable voltage range ?2.25 +7.0 v d accuracy uncalibrated ?200 +200 mv p ovd offset e rrors measured at programmed levels of +7.0 v and ?2.25 v hysteresis 112 mv c b logic output characteristics off state leakage 10 1000 na p disable ov d alarm, apply 3.3 v to ovd pin, measure leakage current maximum on voltage @ 100 a 0.2 0.7 v p activate alarm, force 100 a into ovd pin, measure active alarm voltage propagation delay 1.9 s c b for ovd high: dutx = 0 v to +6 v swing, ovd high = +3.0 v, ovd low = ?2.25 v; for ovd low: dutx = 0 v to +6 v swing, ovd high = +7.0 v, ovd low = +3.0 v 16-bit dac monitor mux table 13. parameter min typ max unit test level test conditions/comments dc characteristics programmable voltage rang e ?2.5 +7.5 v d output resistance 16 k c t pmudac = 0.0 v, fv, i = 0, 200 a; ?v/?i
ADATE304 rev. 0 | page 19 of 52 absolute maximum ratings thermal resistance table 14. parameter rating supply voltages positive supply voltage (v dd to gnd) ?0.5 v to +11.5 v positive v cc supply voltage (v cc to gnd) ?0.5 v to +4.0 v negative supply voltage (v ss to gnd) ?6.25 v to +0.5 v supply voltage difference (v dd to v ss ) ?1.0 v to +16.5 v reference ground (dutgnd to gnd) ?0.5 v to +0.5 v agnd to dgnd ?0.5 v to +0.5 v vplus supply voltage (v plus to gnd) ?0.5 v to +17.5 v input voltages input common-mode voltage v ss to v dd short-circuit voltage 1 ?3.0 v to +8.0 v high speed input voltage 2 0.0 v to v cc high speed differential input voltage 3 0.0 v to v cc vref ?0.5 v to +5.5 v dutx i/o pin current dcl maximum short-circuit current 4 140 ma temperature operating temperature, junction 125c storage temperature range ?65c to +150c table 15. thermal resistance package type ja jc 84-ball csp_bga 31.1 0.51 explanation of test levels d definition s design verification simulation p 100% production tested p f functionally checked during production test c t characterized on tester c b characterized on bench esd caution 1 r l = 0 , v dut continuous short-circuit condition (vh, vl, vt, high-z, vcom, clamp modes). 2 dataxp, dataxn, rcvxp, rcvxn, under source r l = 0 . 3 dataxp to dataxn, rcvxp, rcvxn. 4 r l = 0 , vdutx = C3 v to +8 v; dcl current limit. continuous short-circuit condition. ADATE304 must current limit and survive continuous short circuit. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADATE304 rev. 0 | page 20 of 52 pin configuration and fu nction descriptions a b c 1 098765432 1 d e f g h j k hvout pmus_ch0 vsso_0 (drive) dut0 vddo_0 (drive) vddo_1 (drive) dut1 vsso_1 (drive) pmus_ch1 tempsense vplus scap0 vss agnd vdd vdd agnd vss scap1 vdd/vdd_ tmpsns ffcap_0b agnd data0n vss vdd vdd vss data1n agnd ffcap_1b ovd_ch0 vdd data0p data1p vdd ovd_ch1 ffcap_0a vss rcv0n rcv1n vss ffcap_1a agnd agnd rcv0p rcv1p agnd agnd comp_ql0p comp_ql0n comp_vtt0 comp_vtt1 comp_ql1n comp_ql1p comp_qh0p comp_qh0n agnd vss vdd vdd vss agnd comp_qh1n comp_qh1p agnd agnd agnd rst sdin dgnd dac16_mon agnd agnd agnd vref_gnd vref agnd vcc sclk sdout cs agnd dutgnd measout01/ tempsense 07279-002 figure 2. pin configuration
ADATE304 rev. 0 | page 21 of 52 table 16. pin function descriptions pin no. mnemonic description a1 tempsense temperature sense output a2 pmus_ch1 pmu external sense path channel 1 a3 vsso_1 (drive) driver output supply (?5.0 v) channel 1 a4 dut1 device under test channel 1 a5 vddo_1 (drive) driver outp ut supply (+10.75 v) channel 1 a6 vddo_0 (drive) driver outp ut supply (+10.75 v) channel 0 a7 dut0 device under test channel 0 a8 vsso_0 (drive) driver output supply (?5.0 v) channel 0 a9 pmus_ch0 pmu external sense path channel 0 a10 hvout high voltage driver output b1 vdd/vdd_tmpsns temperature sense supply (+10.75 v) b2 scap1 pmu stability capacitor connection channel 1 (330 pf) b3 vss supply (?5.0 v) b4 agnd analog ground b5 vdd supply (+10.75 v) b6 vdd supply (+10.75 v) b7 agnd analog ground b8 vss supply (?5.0 v) b9 scap0 pmu stability capacitor connection channel 0 (330 pf) b10 vplus supply (+16.75 v) c1 ffcap_1b pmu feedforward capacitor connection b channel 1 (220 pf) c2 agnd analog ground c3 data1n driver data input (negative) channel 1 c4 vss supply (?5.0 v) c5 vdd supply (+10.75 v) c6 vdd supply (+10.75 v) c7 vss supply (?5.0 v) c8 data0n driver data input (negative) channel 0 c9 agnd analog ground c10 ffcap_0b pmu feedforward capacitor connection b channel 0 (220 pf) d1 ovd_ch1 overvoltage detection flag output channel 1 d2 vdd supply (+10.75 v) d3 data1p driver data input (positive) channel 1 d8 data0p driver data input (positive) channel 0 d9 vdd supply (+10.75 v) d10 ovd_ch0 overvoltage detection flag output channel 0 e1 ffcap_1a pmu feedforward capacitor connection a channel 1 (220 pf) e2 vss supply (?5.0 v) e3 rcv1n receive data input (negative) channel 1 e8 rcv0n receive data input (negative) channel 0 e9 vss supply (?5.0 v) e10 ffcap_0a pmu feedforward capacitor connection a channel 0 (220 pf) f1 agnd analog ground f2 agnd analog ground f3 rcv1p receive data input (positive) channel 1 f8 rcv0p receive data input (positive) channel 0 f9 agnd analog ground f10 agnd analog ground g1 comp_ql1p low-side comparator output (positive) channel 1 g2 comp_ql1n low-side comparator output (negative) channel 1 g3 comp_vtt1 comparator supply termination channel 1 g8 comp_vtt0 comparator supply termination channel 0
ADATE304 rev. 0 | page 22 of 52 pin no. mnemonic description g9 comp_ql0n low-side comparator output (negative) channel 0 g10 comp_ql0p low-side comparator output (positive) channel 0 h1 comp_qh1p high-side comparator output (positive) channel 1 h2 comp_qh1n high-side comparator output (negative) channel 1 h3 agnd analog ground h4 vss supply (?5.0 v) h5 vdd supply (+10.75 v) h6 vdd supply (+10.75 v) h7 vss supply (?5.0 v) h8 agnd analog ground h9 comp_qh0n high-side comparator output (negative) channel 0 h10 comp_qh0p high-side comparator output (positive) channel 0 j1 agnd analog ground j2 agnd analog ground j3 agnd analog ground j4 dac16_mon 16-bit dac monitor mux output j5 dgnd digital ground j6 sdin serial peripheral interface (spi) data in j7 rst serial peripheral interface (spi) reset j8 agnd analog ground j9 agnd analog ground j10 agnd analog ground k1 measout01/tempsense muxed output shared by pmu measout channel 0, pmu measout channel 1/ temperature sense and temperature sense gnd reference k2 dutgnd dut ground reference k3 agnd analog ground k4 cs serial peripheral interface (spi) chip select k5 sdout serial peripheral interface (spi) data out k6 sclk serial peripheral interface (spi) clock k7 vcc supply (+3.3 v) k8 agnd analog ground k9 vref +5 v dac reference voltage k10 vref_gnd dac ground reference
ADATE304 rev. 0 | page 23 of 52 typical performance characteristics 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 5.0 4.03.5 2.5 3.0 2.01.51.00.5 0 time (ns) voltage (v) 4.5 1v 2v 3v 07279-006 0.30 0.25 0.20 0.15 0.10 0.05 0 ?0.05 0 2 4 6 8 10 12 14 18 20 time (ns) voltage (v) 16 0.2v 0.5v 07279-003 figure 3. driver small signal response; vh = 0.2 v, 0.5 v; vl = 0.0 v; 50 termination figure 6. 50 mhz driver response; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v, 50 termination 1.8 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 voltage (v) 1.4 02 0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 19 20 0 23456789101112131415161718 time (ns) voltage (v) 1 07279-007 1v 2v 3v 18 16 1412 10 8642 time (ns) 1v 2v 07279-004 3v figure 7. 100 mhz driver response; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination figure 4. driver large signal response; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination 6 5 4 3 2 1 0 ?1 voltage (v) 02 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 10 987654321 time (ns) voltage (v) 1v 2v 3v 07279-008 16 18 141210 8642 time (ns) 1v 5v 3v 07279-005 figure 8. response at 200 mh; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination figure 5. driver large signal response; vh = 1.0 v, 3.0 v, 5.0 v; vl = 0.0 v; 500 termination
ADATE304 rev. 0 | page 24 of 52 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 03 12 4 5 678 10 9 time (ns) voltage (v) 1v 2v 3v 0.5v 0 7279-009 figure 9. 300 mhz driver response; vh = 0.5 v, 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (ns) voltage (v) 1v 2v 0.5v 07279-010 figure 10. 400 mhz driver response; vh = 0.5 v, 1.0 v, 2.0 v, vl = 0.0 v; 50 termination 1.2 1.0 0.8 0.6 0.4 0.2 0 200 250 300 350 frequency (mhz) voltage (v) 07279-011 figure 11. driver toggle rate, vh = 2. 0 v, vl = 0.0 v, 50 termination 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 voltage (v) time (ns) 19 16141210 864 22 17151311 975310 0 18 07279-012 figure 12. driver active (vh and vl) to and from vterm transition; vh = 1.0 v, vt = 0.5 v, vl = 0.0 v 1.2 1.0 0.8 0.6 0.4 0.2 ?0.2 0 voltage (v) time (ns) 19 16141210 864 22 17151311 975310 0 18 07279-013 figure 13. driver active (vh and vl) to and from vterm transition; vh = 2.0 v, vt = 1.0 v, vl = 0.0 v 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 voltage (v) 0 time (ns) 2018161412 10 8642 07279-014 figure 14. driver active (vh and vl) to and from vterm transition; vh = 3.0 v, vt = 1.5 v, vl = 0.0 v
ADATE304 rev. 0 | page 25 of 52 ?20 ?40 ?60 ?80 0 20 123 4 5 6 7 8 pulsewidth (ns) trailing edge error (ps) 9 1 0 0.2v neg 0.2v pos 07279-015 figure 15. driver minimum pulse width; vh = 0.2 v, vl = 0.0 v ?20 ?40 ?80 ?60 0 20 123 4 5 6 7 8 pulsewidth (ns) trailing edge error (ps) 9 1 0 0.5v neg 0.5v pos 07279-016 figure 16. driver minimum pulse width; vh = 0.5 v, vl = 0.0 v 0 ?20 ?40 ?60 ?80 ?100 20 123 4 5 6 7 8 pulsewidth (ns) trailing edge error (ps) 9 1 0 1v neg 1v pos 07279-017 figure 17. driver minimum pulse width; vh = 1.0 v, vl = 0.0 v 0 ?20 ?40 ?60 ?80 ?100 20 123 4 5 6 7 8 pulsewidth (ns) trailing edge error (ps) 9 1 0 2v pos 07279-018 2v neg figure 18. driver minimum pulse width; vh = 2.0 v, vl = 0.0 v ?20 ?40 ?60 ?80 ?100 20 0 123 4 5 6 7 8 pulse width (ns) trailing edge error (ps) 9 1 0 3v neg 3v pos 07279-019 figure 19. driver minimum pulse width; vh = 3.0 v, vl = 0.0 v 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2 ?1 0 1 2 3 4 5 6 7 driver output voltage (v) linearity error (mv) 07279-020 figure 20. driver vh linearity error
ADATE304 rev. 0 | page 26 of 52 1.0 0.5 0 ?1.0 ?0.5 ?1.5 ?2?10123456 driver output voltage (v) linearity error (mv) 07279-021 figure 21. driver vl linearity error 0.8 0.6 0.2 ?0.2 0.4 0 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?2?101234567 driver output voltage (v) linearity error (mv) 07279-022 figure 22. driver vt linearity error 48.0 47.6 47.2 46.8 46.4 47.8 47.4 47.0 46.6 46.2 ?60 ?40 ?20 0 20 40 60 driver output current (ma) driver output resistance ( ? ) 0 7279-023 figure 23. driver output resistance vs. output current 120 80 100 60 40 20 0 ?20 ?2?1012345 7 6 v dutx (v) driver output current (ma) 07279-024 figure 24. driver output current limit; driver programmed to ?1.25 v; v dutx swept from ?1.25 v to +6.75 v 20 ?20 0 ?40 ?60 ?80 ?120 ?100 ?2?1012345 7 6 v dutx (v) driver output current (ma) 0 7279-025 figure 25. driver output current limit; driver programmed to 6.75 v; v dutx swept from ?1.25 v to +6.75 v 8 7 5 3 6 4 2 1 0 ?1 ?2 ?3 ?101 2 3 45 6 vl programmed voltage (v) linearity error (mv) 07279-026 figure 26. hvout vl linearity error
ADATE304 rev. 0 | page 27 of 52 3 1 2 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 567891011121314 vl programmed voltage (v) linearity error (mv) 07279-027 figure 27. hvout vhh linearity error 70 80 60 50 40 30 20 10 0 ?10 ?101 2 3 45 6 v hvout (v) hvout driver current (ma) 07279-028 figure 28. hvout vh current limit; vh = ?0.1 v; v hvout swept from ?0.1 v to +6.0 v 80 60 40 20 0 ?20 ?40 ?60 ?80 5 6 7 8 9 101112131415 v hvout (v) hvout driver current (ma) 07279-029 figure 29. hvout vhh current limit; vhh = 10.0 v; v hvout swept from ?5.9 v to +14.1 v 1.0 0.8 0.6 0.4 0.2 0 0 0.6 1.2 1.8 2.4 3.0 time (ns) voltage (v) rise input fall input rise shmoo fall shmoo 07279-030 figure 30. comparator shmoo, 1.0 v input, 0.7 ns (10% to 90%) input, 50 terminated 1.0 0.8 0.6 0.4 0.2 0 0 0.6 1.2 1.8 2.4 3.0 time (ns) voltage (v) rise input fall input rise shmoo fall shmoo 07279-031 figure 31. comparator shmoo, 1.5 v input, 1.0 ns (10% to 90%) input, 50 terminated 1.6 1.2 0.8 0.4 0 0 0.6 1.2 1.8 2.4 3.0 time (ns) voltage (v) rise input fall input rise shmoo fall shmoo 07279-032 figure 32. comparator shmoo, 1.5 v input, 1.0 ns (10% to 90%) input, 50 terminated
ADATE304 rev. 0 | page 28 of 52 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 10 123 4 5 6 7 8 pulsewidth (ns) trailing edge error (ps) 9 1 0 1v pos 07279-035 1v neg figure 33. comparator minimum pulse width, 1.0 v 100 75 50 25 0 ?25 ?50 0.5 1.0 1.5 2.0 2.5 input slewrate (10%-90%) (ns) propagation delay variation (ps) rising falling total 07279-036 figure 34. comparator slew rate dispersion, input swing = 1.5 v, comparator threshold = 0.75 v 1.8 1.4 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0 voltage (v) 0 5 10 15 20 25 30 35 40 45 50 time (ns) 07279-037 figure 35. comparator output waveform, comp_qh0p, comp_qh0n 0.6 0.4 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 ?1.4 ?1.2 ?1.6 ?2?101234567 programmed threshold voltage (v) linearity error (mv) 07279-038 figure 36. comparator threshold linearity ? 2.5 ?2.6 ?2.7 ?2.8 ?2.9 ?3.0 ?3.1 ?3.2 ?2 ?1 0 1 2 3 4 5 input common-mode voltage (v) differential comparator offset (mv) 07279-039 figure 37. differential comparator cmrr 15 10 5 0 ?10 ?5 ?15 ?2 ?1 0 1 2 3 4 5 6 v dutx (v) load current (ma) 07279-040 figure 38. active load commutation response; vcom = 2.0 v; ioh = iol = 12 ma
ADATE304 rev. 0 | page 29 of 52 6 4 2 0 ?2 ?4 ?6 024681012 active load current (ma) linearity error (a) 07279-041 figure 39. active load current linearity 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.8 ?1.2 ?0.6 ?1.0 ?1.4 ?1 0 1 2 3 4 5 6 7 vcom voltage (v) linearity error (mv) 07279-042 figure 40. active lo ad vcom linearity 6.0 5.5 5.0 4.0 4.5 3.5 3.0 ?2?101234567 v dutx (v) i dutx (na) 07279-043 figure 41. dutx pin leakage in low leakage mode 6 5 4 2 3 1 0 ?2 ?1 0 1 2 3 4 5 7 6 v dutx (v) i dutx (na) 07279-044 figure 42. dutx pin leakage in high-z mode 40 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?40 ?30 ?20 ?10 0 10 20 30 40 pmu output current (ma) linearity error (a) 0 7279-045 figure 43. pmu force current range a linearity 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 pmu output current (ma) linearity error (a) 07279-046 figure 44. pmu force current range b linearity
ADATE304 rev. 0 | page 30 of 52 0.06 0.04 0.02 ?0.02 0 ?0.04 ?0.06 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 pmu output current (ma) linearity error (a) 07279-047 figure 45. pmu force current range c linearity 0.006 0.004 0.002 ?0.002 0 ?0.004 ?0.006 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 pmu output current (ma) linearity error (a) 0 7279-048 figure 46. pmu force current range d linearity 0.0006 0.0004 0.0002 0 ?0.0002 ?0.0006 ?0.0004 ?0.0008 ?0.0020 ?0.0015 ?0.0010 ?0.0050 0 0.0050 0.0010 0.0015 0.0020 pmu output current (ma) linearity error (a) 07279-049 figure 47. pmu force current range e linearity 4 3 2 1 0 ?1 ?2 ?3 ?4 ?40 ?30 ?20 ?10 0 10 20 30 40 i dutx (ma) pmu voltage error (mv) 0 7279-050 figure 48. pmu force voltage range a output voltage error at 6.75 v vs. output current 4 3 2 1 0 ?1 ?2 ?3 ?4 ?40 ?30 ?20 ?10 0 10 20 30 40 i dutx (ma) pmu voltage error (mv) 0 7279-051 figure 49. pmu fv range a outp ut voltage error at ?1.25 v vs. output current 0.6 0.4 0.2 0 ?0.4 ?0.2 ?0.6 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 i dutx (ma) pmu voltage error (mv) 07279-052 figure 50. pmu fv range b output voltag e error at 6.75 v vs. output current
ADATE304 rev. 0 | page 31 of 52 i dutx (ma) pmu voltage error (mv) 0 7279-053 0.6 0.4 0.2 0 ?0.4 ?0.2 ?0.6 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 figure 51. pmu fv range b outp ut voltage error at ?1.25 v vs. output current 5 0 ?5 ?10 ?20 ?15 ?25 ?30 ?2?1012345 7 6 v dutx (v) pmu current error (a) 07279-054 figure 52. pmu fi range a output cu rrent error at ?32 ma vs. output voltage; output voltage is pulled externally 10 0 ?10 ?30 ?70 ?50 ?20 ?40 ?60 ?80 ?90 ?2?101234567 v dutx (v) pmu current error (a) 07279-055 figure 53. pmu fi range a output cu rrent error at +32 ma vs. output voltage; output voltage is pulled externally 0.7 0.6 0.4 0.5 0.3 0.1 0.2 0 ?0.1 ?2 ?1 0 1 2 3 4 5 6 7 v dutx (v) pmu current error (a) 07279-056 figure 54. pmu fi range b output curren t error at ?2 ma vs. output voltage; output voltage is pulled externally 0.7 0.5 0.6 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?2 ?1 0 1 2 3 4 5 6 7 v dutx (v) pmu current error (a) 07279-057 figure 55. pmu fi range b output curren t error at +2 ma vs. output voltage; output voltage is pulled externally 0.0025 0.0015 0.0020 0.0010 0.0005 0 ?0.0010 ?0.0005 ?2?101234567 v dutx (v) pmu current error (a) 07279-058 figure 56. pmu fi range e output curren t error at ?2 a vs. output voltage; output voltage is pulled externally
ADATE304 rev. 0 | page 32 of 52 0.0020 0.0015 0.0010 0.0005 0 ?0.0005 ?2?1012345 7 6 v dutx (v) pmu current error (a) 07279-059 (500ps/div) c1 (100mv/div) 07279-062 figure 57. pmu fi range e output curren t error at +2 a vs. output voltage; output voltage is pulled externally figure 60. eye diagram, 400 mbps, prbs31; vh = 1.0 v, vl = 0.0 v (200ps/div) c1 (100mv/div) 07279-063 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?2 ?1 0 1 2 3 4 5 v dutx (v) pmu voltage error (mv) 07279-060 figure 61. eye diagram, 600 mbps, prbs31; vh = 1.0 v, vl = 0.0 v figure 58. pmu measure current range b cmrr, externally pulling 1 ma, fvmi (500ps/div) c1 (200mv/div) 07279-065 (1ns/div) c1 (100mv/div) 07279-061 figure 59. eye diagram, 200 mbps, prbs31; vh = 1.0 v, vl = 0.0 v figure 62. eye diagram, 400 mbps, prbs31; vh = 2.0 v, vl = 0.0 v
ADATE304 rev. 0 | page 33 of 52 spi details sclk cs sdin t ch t cl t cssa t csha t cshd t cssd t dh t ds t csw sdout do_2 last do_12 last do_13 last do_14 last do_15 last do_1 last do_0 last t do data[14] data[15] ch[1] r/w addr[1] addr[0] 0 7279-067 figure 63. spi timing diagram table 17. serial peripheral interface timing requirements symbol parameter min max unit t ch sclk minimum high 9.0 ns t cl sclk minimum low 9.0 ns t csha cs assert hold 3.0 ns t cssa cs assert setup 3.0 ns t cshd cs deassert hold 3.0 ns t cssd cs deassert setup 3.0 ns t dh sdin hold 3.0 ns t ds sdin setup 3.0 ns t do sdout data out 15.0 ns t csw cs minimum between assertions 1 2 sclk cycles cs minimum directly after a read request 3 sclk cycles t cstp minimum delay after cs is deasserted before sclk can be stopped (not shown in ); this allows any internal operations to complete figure 63 16 sclk cycles 1 an extra cycle is needed after a read request to prime the read data into the spi shift register.
ADATE304 rev. 0 | page 34 of 52 definition of spi word the spi can accept variable length words, depending on the operation. at most, the word length equals 24 bits: 16 bits of data, two channel selects, one read/write (r/w) selector, and a 5-bit address. depending on the operation, the data can be smaller or, in the case of a read operation, nonexistent. table 18. channel selection channel 1 channel 0 channel selected 0 0 nop (no channel selected, no register changes) 0 1 channel 0 selected 1 0 channel 1 selected 1 1 channel 0 and channel 1 selected table 19. r/w definition r/w description 0 current register specified by address shifts out of sdout on next shift operation 1 current data written to the register specified by address and channel select example 1: 16-bit write write 16 bits of data to a register or dac; ignore unused msbs. for example, bit 15 and bit 14 are ignored, and bit 13 through bit 0 are applied to the 14-bit dac. 07279-068 data[15:0] ch[1:0] r/w addr[4:0] figure 64. 16-bit write example 2: 14-bit write write 14 bits of data to the dac. 9 -06 data[13:0] ch[1:0] r/w addr[4:0] 07279 figure 65. 14-bit write example 3a: 2-bit write write two bits of data to the 2-bit register. data[1:0] ch[1:0] r/w addr[4:0] 07279-070 figure 66. 2-bit write example 3b: 2-bit write write two bits of data to the 2-bit register. bit 15 through bit 2 are ignored and bit 1 through bit 0 are applied to the regis ter. data[15:0] ch[1:0] r/w addr[4:0] 07279-071 figure 67. 2-bit write example 4: read request read request and follow with a second instruction (could be nop) to clock out the data. data[15:0] ch[1:0] r/w addr[4:0] ch[1:0] r/w = 0 addr[4:0] 07279-072 figure 68. read request
ADATE304 rev. 0 | page 35 of 52 write operation 0 232221 20 191817 16 151413 12 24 25 notes 1. r/w = 1. 2. x = don?t care. data[14] data[15] data[13] data[2] data[1] data[0] ch[ 1] ch[ 0] addr[3] addr[1] addr[4] addr[2] addr[0] x r/w sclk input sdin input cs input sdout output x 07279-073 figure 69. 16-bit spi write 0 11 10 987654 123 data[1] data[0] ch[1] ch[ 0] addr[4] addr[3] addr[2] addr[1] addr[0] r/w sclk input sdin input sdout output x x cs input notes 1. r/w = 1. 2. x = don?t care. 07279-074 figure 70. 2-bit spi write
ADATE304 rev. 0 | page 36 of 52 read operation the read operation is a two-stage operation. first, a word is shifted in, specifying which register to read. cs is deasserted for three clock cycles, and then a second word is shifted in to obtain the readback data. this second word can be either another operation or an nop address. if another operation is shifted in, it must shift in at least eight bits of data to read back the previous specified data. the nop address can be used for this read if there is no need to read/write another register. to maintain the clarity of the operation, it is strongly recommended that the nop address be used for all reads. any register read that is fewer than 16 bits has zeros filled in the top bits to make it a 16-bit word. x x read instruction nop x read data x sclk input sdin input sdout output cs input notes 1. x = don?t care. 0 7279-075 figure 71. spi read overview x data[15:0], value is a don?t care 0 25 24 23 22 21 20 19 1817 16 15 1413 12 ch[1] x r/w ch[0] addr[4] addr[3] addr[2] addr[1] addr[0] sclk input sdin input sdout output cs input notes 1. x = don?t care. 07279-076 figure 72. spi readdetails of read request x data[15:0], value is a don?t care 0 25 24 23 22 21 20 19 18 17 16 15 1413 12 ch[1] rdata[2] rdata[1] rdata[15] rdata[14] rdata[0] x r/w = 1 addr[4:0] = 0x00 (nop) ch[0] sclk input sdin input sdout output cs input notes 1. rdata is the register value being read. 2. x = don?t care. 07279-077 figure 73. spi readdetails of read out
ADATE304 rev. 0 | page 37 of 52 reset operation the ADATE304 contains an asynchronous reset feature. the ADATE304 can be reset to the default values shown in table 2 0 by utilizing the rst pin. to initiate the reset operation, deassert the rst pin for a minimum of 100 ns and deassert the cs pin for a minimum of two sclk cycles. rst cs sclk 100ns minimum minimum of two sclk edges after asserting rst before resuming normal operation. 07279-078 figure 74. reset operation
ADATE304 rev. 0 | page 38 of 52 register map the addr[4:0] bits determine the destination register of the data being written to the ADATE304. table 20. register selection data[15:0] ch[1:0] r/w addr[4:0] register selected reset state n/a 1 n/a n/a 0x00 nop n/a data[13:0] ch[1:0] r/w 0x01 vh dac level 4096d data[13:0] ch[1:0] r/w 0x02 vl dac level 4096d data[13:0] ch[1:0] r/w 0x03 vt/vcom dac level 4096d data[13:0] ch[1:0] r/w 0x04 vol dac level 4096d data[13:0] ch[1:0] r/w 0x05 voh dac level 4096d data[13:0] ch[1:0] r/w 0x06 vch dac level 4096d data[13:0] ch[1:0] r/w 0x07 vcl dac level 4096d data[13:0] ch[1:0] r/w 0x08 v(ioh ) dac level 4096d data[13:0] ch[1:0] r/w 0x09 v(iol ) dac level 4096d data[13:0] ch[1] r/w 0x0a ovd high level 4096d data[13:0] ch[0] r/w 0x0a ovd low level 4096d data[15:0] ch[1:0] r/w 0x0b pmudac level 16384d data[2:0] ch[1:0] r/w 0x0c pe/pmu enable 000b data[2:0] ch[1:0] r/w 0x0d channel state 000b data[9:0] ch[1:0] r/w 0x0e pmu state 0d data[2:0] ch[1:0] r/w 0x0f pmu measure enable 000b data[0] ch[1:0] r/w 0x10 differential comparator enable 0b data[1:0] ch[1:0] r/w 0x11 16-bit dac monitor 00b data[1:0] ch[1:0] r/w 0x12 ovd_chx alarm mask 01b data[2:0] ch[1:0] r 0x13 ovd_chx alarm state n/a n/a n/a n/a 0x14 to 0x1f reserved n/a 1 n/a means not applicable.
ADATE304 rev. 0 | page 39 of 52 details of registers table 21. pe/pmu enab le (addr[4:0] = 0x0c) bit name description data[2] pmu enable 0 = disable pmu force output and clamps, place pmu in mv mode 1 = enable pmu force output when set to 0, the pmu state bits are ignored, except for the pmu sense path (data[7]) data[1] force vt 0 = normal driver operation 1 = force driver to v t see table 29 for complete functionality of this bit data[0] pe disable 0 = enable driver functions 1 = disable driver (low leakage) see table 29 for complete functionality of this bit table 22. channel state (addr[4:0] = 0x0d) bit name description data[2] hv mode select 0 = hv driver in low impedance. 1 = enable hv driver. this bit affects channel 0 only. ensure that the channel 0 bit in spi write is active. channel 1 bit in spi write is dont care. data[1] load enable 0 = disable load. 1 = enable load. see table 29 for complete functionality of this bit. data[0] driver high-z or vt 0 = enable driver high-z function. 1 = enable driver vterm function. see table 29 for complete functionality of this bit. table 23. pmu state (addr[4:0] = 0x0e) 1 , 2 bit name description data[9:8] pmu input selection 00 = v dutgnd (calibrated for 0.0 v voltage reference) 01 = 2.5 v + v dutgnd (calibrated for 0.0 a current reference) 1x = pmudac data[7] pmu sense path 0 = internal sense 1 = external sense data[6] reserved data[5] pmu clamp enable 0 = disable clamps 1 = enable clamps data[4] pmu measure voltage or current 0 = measure voltage mode 1 = measure current mode data[3] pmu force voltage or current 0 = force voltage mode 1 = force current mode data[2:0] pmu range 0xx = 2 a range 100 = 20 a range 101 = 200 a range 110 = 2 ma range 111 = 32 ma range 1 note that when addr[4:0] = 0x0c , the pmu enable bit (data[2]) = 0, pmu force ou tputs and clamps are disabled, and the pmu is p laced into measure voltage mode. pmu state data[9:8] and data[6:0] are ignored, and only the data[7] pmu sense path is valid. 2 x means dont care.
ADATE304 rev. 0 | page 40 of 52 table 24. pmu measure enable (addr[4:0] = 0x0f) 1 bit name description data[2:1] measout01 select 00 = pmu measout channel 0 01 = pmu measout channel 1 10 = temperature sensor ground reference 11 = temperature sensor data[0] measout01 output enable 0 = measout01 is tristated 1 = measout01 is enabled 1 this register is written to or read from when either of the ch[1:0] bits is 1. table 25. differential comparat or enable (addr[4:0] = 0x10) 1 bit name description data[0] differential comparator enable 0 = differential comparator is disabled; the channel 0 normal window comparator (nwc) outputs are located on channel 0 1 = differential comparator is enabled; the differential comparator outputs are located on channel 0 1 this register is written to or read from when either of the ch[1:0] bits is 1. table 26. dac16_mon (16-bit dac monitor) (addr[4:0] = 0x11) 1 bit name description data[1] 16-bit dac mux enable 0 = 16-bit dac mux is tristated 1 = 16-bit dac mux is enabled data[0] 16-bit dac mux select 0 = 16-bit dac channel 0 1 = 16-bit dac channel 1 1 this register is written to or read from when either of the ch[1:0] bits is 1. table 27. ovd_chx alarm mask (addr[4:0] = 0x12) bit name description data[1] pmu mask 0 = disable pmu alarm flag 1 = enable pmu alarm flag data[0] ovd mask 0 = disable ovd alarm flag 1 = enable ovd alarm flag table 28. ovd_chx alarm state (addr[4:0] = 0x13) 1 bit name description data[2] pmu clamp flag 0 = pmu is not clamped 1 = pmu is clamped data[1] ovd high flag 0 = dut voltage < ovd high voltage 1 = dut voltage > ovd high voltage data[0] ovd low flag 0 = dut voltage > ovd low voltage 1 = dut voltage < ovd low voltage 1 this register is a read-only register.
ADATE304 rev. 0 | page 41 of 52 user information power supply considerations power supply sequencing it is recommended that the power supplies be brought up in the following order: 1. grounds (dgnd, agnd, vref_gnd) 2. v ss 3. v cc , v comp_vtt , and v ref 4. v dd 5. v plus if the hvout pin is not used, the v plus supply can be connected to v dd . power supply decoupling t he ADATE304 is a high performance device that requires close attention to power supply decoupling to deliver the best performance. the use of full power planes with low inductance capacitors placed as close to the power pins as possible is recom- mended. the following power connections are the most important: ? vplus to agnd (for the hvout driver) ? vdd to vss near the dutx pin (for the driver) ? vdd and vss to agnd near the dutx pin (for the comparators) ? vcc to dgnd (for the digital) additionally, large bulk capacitors (that is, 10 f) should be used on every power supply on the printed circuit board (pcb). truth tables table 29. driver and load truth table 1 registers signals driver state load state pe disable data[0] addr[4:0] = 0x0c force vt data[1] addr[4:0] = 0x0c load enable data[1] addr[4:0] = 0x0d driver high-z/vt data[0] addr[4:0] = 0x0d datax rcvx 1 x x x x x high-z without clamps power-down 0 1 x x x x vt power-down 0 0 0 0 0 0 vl power-down 0 0 0 0 0 1 high-z with clamps power-down 0 0 0 0 1 0 vh power-down 0 0 0 0 1 1 high-z with clamps power-down 0 0 0 1 0 0 vl power-down 0 0 0 1 0 1 vt power-down 0 0 0 1 1 0 vh power-down 0 0 0 1 1 1 vt power-down 0 0 1 0 0 0 vl active off 0 0 1 0 0 1 high-z with clamps active on 0 0 1 0 1 0 vh active off 0 0 1 0 1 1 high-z with clamps active on 0 0 1 1 0 0 vl active on 0 0 1 1 0 1 high-z with clamps active on 0 0 1 1 1 0 vh active on 0 0 1 1 1 1 high-z with clamps active on 1 x means dont care. table 30. hvout truth table 1 hvout mode select data[2] addr[4:0] =0x0d channel 0 rcv channel 0 data hvout driver output 1 1 x vhh mode; vhh = (vt + 1 v) 2 + dutgnd (channel 0 vt dac) 1 0 0 vl (channel 0 vl dac) 1 0 1 vh (channel 0 vh dac) 0 x x disabled (hvout pin set to 0 v low impedance) 1 x means dont care.
ADATE304 rev. 0 | page 42 of 52 table 31. comparator truth table differential comparator enable data[0] addr[4:0] = 0x10 comp_qh0 comp_ql0 comp_qh1 comp_ql1 0 normal window mode normal window mode normal window mode normal window mode logic high: voh0 < v dut0 logic high: vol0 < v dut0 logic high: voh1 < v dut1 logic high: vol1 < v dut1 logic low: voh0 > v dut0 logic low: vol0 > v dut0 logic low: voh1 > v dut1 logic low: vol1 > v dut1 1 differential comparator mode differential comparat or mode normal window mode normal window mode logic high: voh0 < v dut0 ? v dut1 logic high: vol0 < v dut0 ? v dut1 logic high: voh1 < v dut1 logic high: vol1 < v dut1 logic low: voh0 > v dut0 ? v dut1 logic low: vol0 > v dut0 ? v dut1 logic low: voh1 > v dut1 logic low: vol1 > v dut1
ADATE304 rev. 0 | page 43 of 52 details of dacs vs. levels t here are ten 14-bit dacs per channel. these dacs provide levels for the driver, comparator, load currents, vhh buffer, ovd, and clamp levels. there are three versions of output levels as follows: ? ?2.5 v to +7.5 v and tracks dutgnd. controls the vh, vl, vt/vcom/vhh, voh, vol, vch, and vcl levels. ? ?3.0 v to +7.0 v and tracks dutgnd. controls the ovd levels. ? ?2.5 v to +7.5 v and does not track dutgnd. controls the ioh and iol levels. there is one 16-bit dac per channel. this dac provides the levels for the pmu. the output level is as follows: ? ?2.5 v to +7.5 v and tracks dutgnd; controls the pmu levels. table 32. level transfer functions dac transfer function programmable range 1 (all 0s to all 1s) levels v out = 2.0 ( v ref ? v ref_gn d ) ( cod e/(2 14 )) ? 0.5 ( v ref ? v ref_gnd ) + v dutgnd code = [ v out ? v dutgnd + 0.5 ( v ref ? v ref_gnd )] [(2 14 )/(2.0 ( v ref ? v ref_gnd ))] ?2.5 v to +7.5 v vh, vl, vt/vcom, vol, voh, vch, vcl v out = 4.0 (v ref ? v ref_gnd ) ( code /(2 14 )) ? 1.0 ( v ref ? v ref_gnd ) + 2.0 + v dutgnd code = [ v out ? v dutgnd ? 2.0 + 1.0 ( v ref ? v ref_gnd )] [(2 14 )/(4.0 ( v ref ? v ref_gnd ))] ?3.0 v to +17.0 v vhh v out = 2.0 ( v ref ? v ref_gnd ) ( code /(2 14 )) ? 0.6 ( v ref ? v ref_gnd ) + v dutgnd code = [ v out ? v dutgnd + 0.6 ( v ref ? v ref_gnd )] [(2 14 )/(2.0 ( v ref ? v ref_gnd ))] ?3.0 v to +7.0 v ovd i out = [2.0 ( v ref ? v ref_gnd ) ( code /(2 14 )) ? 0.5 ( v ref ? v ref_gnd )] (0.012/5.0) code = [( i out (5.0/0.012)) + 0.5 ( v ref ? v ref_gnd )] [(2 14 )/(2.0 ( v ref ? v ref_gnd ))] ?6 ma to +18 ma ioh, iol v out = 2.0 ( v ref ? v ref_gnd ) ( code /(2 16 )) ? 0.5 ( v ref ? v ref_gnd ) + v dutgnd code = [ v out ? v dutgnd + 0.5 ( v ref ? v ref_gnd )] [(2 16 )/(2.0 ( v ref ? v ref_gnd ))] ?2.5 v to +7.5 v pmudac i out = [2.0 ( v ref ? v ref_gnd ) ( code /(2 16 )) ? 0.5 ( v ref ? v ref_gnd ) ? 2.5] (0.050/5.0) code = [( i out (5.0/0.050)) + 2.5 + 0.5 ( v ref ? v ref_gnd )] [(2 16 )/(2.0 ( v ref ? v ref_gnd ))] ?50 ma to +50 ma pmudac (pmu fi range a) i out = [2.0 ( v ref ? v ref_gnd ) ( code /(2 16 )) ? 0.5 ( v ref ? v ref_gnd ) ? 2.5] (0.004/5.0) code = [( i out (5.0/0.004)) + 2.5 + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 ( v ref ? v ref_gnd ))] ?4 ma to +4 ma pmudac (pmu fi range b) i out = [2.0 ( v ref ? v ref_gnd ) ( code /(2 16 )) ? 0.5 ( v ref ? v ref_gnd ) ? 2.5] (0.0004/5.0) code = [( i out (5.0/0.0004)) + 2.5 + 0.5 ( v ref ? v ref_gnd )] [(2 16 )/(2.0 ( v ref ? v ref_gnd ))] ?400 a to +400 a pmudac (pmu fi range c) i out = [2.0 ( v ref ? v ref_gnd ) ( code /(2 16 )) ? 0.5 ( v ref ? v ref_gnd ) ? 2.5] (0.00004/5.0) code = [( i out (5.0/0.00004)) + 2.5 + 0.5 ( v ref ? v ref_gnd )] [(2 16 )/(2.0 ( v ref ? v ref_gnd ))] ?40 a to +40 a pmudac (pmu fi range d) i out = [2.0 ( v ref ? v ref_gnd ) ( code /(2 16 )) ? 0.5 ( v ref ? v ref_gnd ) ? 2.5] (0.000004/5.0) code = [( i out (5.0/0.000004)) + 2.5 + 0.5 ( v ref ? v ref_gnd )] [(2 16 )/(2.0 ( v ref ? v ref_gnd ))] ?4 a to +4 a pmudac (pmu fi range e) 1 programmable range includes a margin outside the specified part performance, allowing fo r offset/gain calibration. table 33. load transfer functions load level transfer function 1 iol v(iol)/5 v 12 ma ioh v(ioh)/5 v 12 ma 1 v(ioh)and v(iol) dac levels are not referenced to dutgnd. table 34. pmu transfer functions pmu mode transfer functions force voltage v out = pmudac measure voltage v measout01 = v dutx (internal sense) or v measout01 = v pmus_chx (external sense) force current i out = [pmudac ? (v ref /2)]/(r 1 5) measure current v measout01 = (v ref /2) + v dutgnd + (i dutx 5 r 1 ) 1 r = 15.5 for range a; 250 for range b; 2.5 k fo r range c; 25 k for range d; 250 k for range e. table 35. pmu user required capacitors capacitor location 220 pf across pin c10 (ffcap_0b) and pin e10 (ffcap_0a) 220 pf across pin c1 (ffcap _1b) and pin e1 (ffcap_1a) 330 pf between gnd and pin b9 (scap0) 330 pf between gnd and pin b2 (scap1)
ADATE304 rev. 0 | page 44 of 52 table 36. temperature sensor temperature output 0 k 0 v 300 k 3 v x k (x k) 10 mv/k table 37. power supply ranges parameter range 1 range 2 nominal vdd +10.75 v +10.0 v nominal vss ?5.00 v ?5.75 v driver vh range ?1.15 v to +6.75 v ?1.9 v to +6.0 v vl range ?1.25 v to +6.65 v ?2.0 v to +5.9 v vt range ?1.25 v to +6.75 v ?2.0 v to +6.0 v functional amplitude 8.0 v 8.0 v reflection clamp vch range ?1.0 v to +6.75 v ?1.0 v to +6.0 v vcl range ?1.25 v to +5.75 v ?2.0 v to +5.0 v comparator input voltage range ?1.25 v to +6.75 v ?2.0 v to +6.0 v active load vcom range ?1.00 v to +6.50 v ?1.75 v to +5.75 v pmu force voltage range ?1.25 v to +6.75 v ?2.0 v to +6.0 v measure voltage range ?1.25 v to +6.75 v ?2.0 v to +6.0 v force current voltage range ?1.25 v to +6.75 v ?2.0 v to +6.0 v measure current voltage range ?1.25 v to +6.75 v ?2.0 v to +6.0 v low clamp range ?1.25 v to +4.75 v ?2.0 v to +4.0 v high clamp range 0.75 v to 6.75 v 0.0 v to 6.0 v ovd ?2.25 v to +7.0 v ?3.0 v to +7.0 v table 38. default test conditions (range 1) name default test condition vh dac level +2.0 v vl dac level +0.0 v vt/vcom dac level +1.0 v vol dac level ?1.0 v voh dac level +6.0 v vch dac level +7.5 v vcl dac level ?2.5 v ioh dac level 0.0 a iol dac level 0.0 a ovd low dac level ?2.5 v ovd high dac level +6.5 v pmudac dac level 0.0 v pe/pmu enable 0x0000: pmu disabled, vt not forced through driver, pe enabled channel state 0x0000: hv mode disabled, load disabled, vterm inactive pmu state 0x0000: i nput of dutgnd, internal sense, clamps disabled, fvmv, range e pmu measure enable 0x0000: measout01 pin tristated differential comparator enable 0x0000: n ormal window comparator mode 16-bit dac monitor 0x0000: dac16_mon tristated ovd_chx alarm mask 0x0000: disable alarm functions data input logic low receive input logic low dutx pin unterminated comparator output unterminated
ADATE304 rev. 0 | page 45 of 52 recommended pmu mode switching sequences t o minimize any possible aberrations and voltage spikes on the dut output, specific mode switching sequences are recommended for the following transitions: ? pmu disable to pmu enable. ? pmu force voltage mode to pmu force current mode. ? pmu force current mode to pmu force voltage mode. pmu disable to pmu enable note that, in table 39 through table 49 , x indicates the dont care bit. step 1. table 39 lists the state of the registers in pmu disabled mode. table 39. register bits setting pe/pmu enable register, addr[4:0] = 0x0c data[2] 0 pmu state register, addr[4:0] = 0x0e data[9:8] xx data[7] x data[6] x data[5] x data[4] x data[3] x data[2:0] xxx step 2. write to register addr[4:0] = 0x0e (see table 40 ). table 40. register bits setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 1x or 00 set desired input selection data[7] x data[6] x data[5] x data[4] x data[3] 0 this bit must be set to force voltage mode to reduce aberrations data[2:0] xxx set desired range step 3. write to register addr[4:0] = 0x0c (see table 41 ). table 41. register bits setting comments pe/pmu enable register, addr[4:0] = 0x0c data[2] 1 pmu is now enabled in force voltage mode pmu force voltage mode to pmu force current mode step 1. table 42 lists the state of registers in force voltage mode. table 42. register bits setting pe/pmu enable register, addr[4:0] = 0x0c data[2] 1 pmu state register, addr[4:0] = 0x0e data[9:8] xx data[7] x data[6] x data[5] x data[4] x data[3] 0 data[2:0] xxx step 2. write to register addr[4:0] = 0x0e (see table 43 ). table 43. register bits setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 01 set 2.5 v + dutgnd input selection data[7] x data[6] x data[5] x data[4] x data[3] 1 set to force current mode data[2:0] 0xx the 2 a range has the minimum offset current step 3. write to register addr[4:0] = 0x0b (see table 44 ). table 44. register bits setting comments vin 16-bit dac, addr[4:0] = 0x0b data[15:0] x update the vin 16-bit dac register to the desired value step 4. write to register addr[4:0] = 0x0e (see table 45 ). table 45. register bits setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 1x set vin input selection data[7] x data[6] x data[5] x data[4] x data[3] 1 data[2:0] xxx set to the desired current range
ADATE304 rev. 0 | page 46 of 52 transition from pmu force current mode to pmu force voltage mode step 1. table 46 lists the state of the registers in force current mode. table 46. register bits setting pe/pmu enable register, addr[4:0] = 0x0c data[2] 1 pmu state register, addr[4:0] = 0x0e data[9:8] xx data[7] x data[6] x data[5] x data[4] x data[3] 1 data[2:0] xxx step 2. write to register addr[4:0] = 0x0e (see table 47 ). table 47. register bits setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 00 set dutgnd input selection data[7] x data[6] x data[5] x data[4] x data[3] 0 set to force voltage mode data[2:0] xxx set to the desired current range step 3. write to register addr[4:0] = 0x0b (see table 48 ). table 48. register bits setting comments vin 16-bit dac, addr[4:0] = 0x0b data[15:0] x update the vin 16-bit dac register to the desired value step 4. write to register addr[4:0] = 0x0e (see table 49 ). table 49. register bits setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 1x set vin input selection data[7] x data[6] x data[5] x data[4] x data[3] 0 force voltage mode data[2:0] xxx
ADATE304 rev. 0 | page 47 of 52 block diagrams rcv vt v cl v ch data vh vl v(iol) v(ioh) dut driver high-z/vt data[0] (addr[4:0] = 0x0d) vt buffer when 1 high-z buffer when 0 force vt data[1] (addr[4:0] = 0x0c) overrides the rcv pin and forces v term mode on the driver and load power-down mode load enable data[1] (addr[4:0] = 0x0d) forces switches open and powers down load when 0 pe disable data[0] (addr[4:0] = 0x0c) forces switch open when 1 r out = 47 ? (trimmed) driver vcom 07279-079 figure 75. driver and load block diagram 48? vl data rcv (shown in rcv = 0 state) vhh = (vt + 1v) 2 + dutgnd vh ~5 ? hv mode select data[2] (addr [4:0] = 0x0d) disables hv driver and forces 0v on hvout when 0 hvout 07279-080 figure 76. hvout dr iver output stage
ADATE304 rev. 0 | page 48 of 52 ? ? ? ? + dut0 ? dut1 2:1 mux differential comparator enable data[0] (addr[4:0] = 0x10) + vol0 v oh0 dut1 dut0? dut1 differential buffer vol0 voh0 vol nwc voh nwc vol dmc voh dmc dut0 comp_qh0 comp_ql0 2:1 mux notes 1. differential comparator only on channel 0. + + 0 7279-081 figure 77. comparator block diagram 50? 50? gnd vtt = 3.3v out high = 1.55v out cm = 1.42v out low = 1.30v 100? receiver comparator output (ab) 07279-082 figure 78. comparator output scheme
ADATE304 rev. 0 | page 49 of 52 2.5 + dutgnd 10k ? 225k ? 2a 20a 200a 2ma 22.5k ? 2.25k ? 250 ? cra = 220pf ffcap_xa ffcap_xb mv 15.5 ? dutx ref in-amp g = 5 measout01 select data[2:1] (addr[4:0] = 0x0f) pmu force v/i data[3] (addr[4:0] = 0x0e) pmu input selection data[9:8] (addr[4:0] = 0x0e) pmu clamp enable data[5] (addr[4:0] = 0x0e) pmu sense p a th d a t a [7] (addr[4:0] = 0x0e) external dut sense pin pmu measure v/i data[4] (addr[4:0] = 0x0e) ch[1] pmu v/i mux mux mux mux mux vch vcl measure v (at output of sense mux) notes 1. switches connected with dotted lines represent pmu range data[2:0] (addr[4:0] = 0x0e); when pmu enable d ata[2] = 0 (addr[4:0 ] = 0x0c), all switches open and pmu powers down. 2. the external sense path must close the loop to enable the clamps to operate correctly. 3. 32ma range has its own output buffer. 4. 32ma buffer tristates when not in use. 330pf scapx (external) 32ma 32ma buffer temp sense gnd ref measure v measure i temp sense vin 2.5v + dutgnd dutgnd measure out measout01 output enable data[0] (addr[4:0] = 0x0f) one per device 07279-083 figure 79. pmu block diagram
ADATE304 rev. 0 | page 50 of 52 pmu v/i clamp flag ?2.5v ovd low level dac (addr[4:0] = 0x0a, ch[0]) (addr[4:0] = 0x12) data[1] pmu mask enables pmu v/i flag to alarm ovd_chx pin ADATE304 (addr[4:0] = 0x12) data[0] ovd mask enables ovd flags to alarm ovd_chx pin ovd_chx short-circuit current = 100a (addr[4:0] = 0x13) 2 data[2] data[1] data[0] 1 the ovd high/low level dac is shared by each channel; therefore, only one ovd high/low voltage level can be set per chip. the ovd dacs provide a voltage range of ?3v to +7v. the recommended high/low settings are +6.5v/?2.5v. (these values need to be programmed by the user upon startup/reset.) 2 this is a read only register that allows the user to determine the cause of the active ovd flag. 6.5v ovd high level dac (addr[4:0] = 0x0a, ch[1]) dut 1 1 0 7279-084 figure 80. ovd block diagram
ADATE304 rev. 0 | page 51 of 52 outline dimensions 091108-a * compliant to jedec standards mo-219 with exception to package height. 0.80 bsc a b c d e f g 987654 2 31 bottom view 7.20 bsc sq h j detail a top view detail a coplanarity 0.12 0.90 ref 0.53 0.48 0.43 0.83 0.76 0.69 0.38 0.33 0.28 ball diameter seating plane 9.10 9.00 sq 8.90 a1 ball corner a1 ball corner * 1.20 1.09 1.00 6.731 ref sq k 10 0.305 ref 0.36 ref figure 81. 84-ball chip scale package ball grid array [csp_bga] (bc-84-2) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADATE304bbcz 1 ?40c to +85c 84-ball chip scale package ball grid array [csp_bga] bc-84-2 1 z = rohs compliant part.
ADATE304 rev. 0 | page 52 of 52 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07279-0-10/08(0)

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